irli520n preliminary hexfet ? power mosfet pd - 9.1496a s d g v dss = 100v r ds(on) = 0.18 w i d =8.1a l logic-level gate drive l advanced process technology l isolated package l high voltage isolation = 2.5kvrms ? l sink to lead creepage dist. = 4.8mm l fully avalanche rated to-220 fullpak fifth generation hexfets from international rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. this benefit, combined with the fast switching speed and ruggedized device design that hexfet power mosfets are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. the to-220 fullpak eliminates the need for additional insulating hardware in commercial-industrial applications. the moulding compound used provides a high isolation capability and a low thermal resistance between the tab and external heatsink. this isolation is equivalent to using a 100 micron mica barrier with standard to-220 product. the fullpak is mounted to a heatsink using a single clip or by a single screw fixing. 3/16/98 description parameter typ. max. units r q jc junction-to-case CCC 5.0 r q ja junction-to-ambient CCC 65 thermal resistance parameter max. units i d @ t c = 25c continuous drain current, v gs @ 10v 8.1 i d @ t c = 100c continuous drain current, v gs @ 10v 5.7 a i dm pulsed drain current ?? 35 p d @t c = 25c power dissipation 30 w linear derating factor 0.20 w/c v gs gate-to-source voltage 16 v e as single pulse avalanche energy ?? 85 mj i ar avalanche current ?? 6.0 a e ar repetitive avalanche energy ? 3.0 mj dv/dt peak diode recovery dv/dt ?? 5.0 v/ns t j operating junction and -55 to + 175 t stg storage temperature range soldering temperature, for 10 seconds 300 (1.6mm from case ) c mounting torque, 6-32 or m3 screw 10 lbf?in (1.1n?m) absolute maximum ratings c/w
irli520n parameter min. typ. max. units conditions v (br)dss drain-to-source breakdown voltage 100 CCC CCC v v gs = 0v, i d = 250a d v (br)dss / d t j breakdown voltage temp. coefficient CCC 0.11 CCC v/c reference to 25c, i d = 1ma ? CCC CCC 0.18 v gs = 10v, i d = 6.0a ? CCC CCC 0.22 w v gs = 5.0v, i d = 6.0a ? CCC CCC 0.26 v gs = 4.0v, i d = 5.0a ? v gs(th) gate threshold voltage 1.0 CCC 2.0 v v ds = v gs , i d = 250a g fs forward transconductance 3.1 CCC CCC s v ds = 25v, i d = 6.0a ? CCC CCC 25 a v ds = 100v, v gs = 0v CCC CCC 250 v ds = 80v, v gs = 0v, t j = 150c gate-to-source forward leakage CCC CCC 100 na v gs = 16v gate-to-source reverse leakage CCC CCC -100 v gs = -16v q g total gate charge CCC CCC 20 i d = 6.0a q gs gate-to-source charge CCC CCC 4.6 nc v ds = 80v q gd gate-to-drain ("miller") charge CCC CCC 10 v gs = 5.0v, see fig. 6 and 13 ?? t d(on) turn-on delay time CCC 40 CCC v dd = 50v t r rise time CCC 35 CCC ns i d = 6.0a t d(off) turn-off delay time CCC 23 CCC r g = 11 w, v gs = 5.0v t f fall time CCC 22 CCC r d = 8.2 w, see fig. 10 ?? between lead, 6mm (0.25in.) from package and center of die contact c iss input capacitance CCC 440 CCC v gs = 0v c oss output capacitance CCC 97 CCC v ds = 25v c rss reverse transfer capacitance CCC 50 CCC ? = 1.0mhz, see fig. 5 ? c drain to sink capacitance CCC 12 CCC ? = 1.0mhz electrical characteristics @ t j = 25c (unless otherwise specified) i gss i dss drain-to-source leakage current s d g l d internal drain inductance CCC 4.5 CCC l s internal source inductance CCC 7.5 CCC r ds(on) static drain-to-source on-resistance nh pf s d g notes: ? repetitive rating; pulse width limited by max. junction temperature. ( see fig. 11 ) ? starting t j = 25c, l = 4.7mh r g = 25 w , i as = 6.0a. (see figure 12) ? t=60s, ?=60hz ? i sd 6.0a, di/dt 340a/s, v dd v (br)dss , t j 175c ? uses irl520n data and test conditions ? pulse width 300s; duty cycle 2%. parameter min. typ. max. units conditions i s continuous source current mosfet symbol (body diode) CCC CCC showing the i sm pulsed source current integral reverse (body diode) ?? CCC CCC p-n junction diode. v sd diode forward voltage CCC CCC 1.3 v t j = 25c, i s = 6.0a, v gs = 0v ? t rr reverse recovery time CCC 110 160 ns t j = 25c, i f = 6.0a q rr reverse recovery charge CCC 410 620 nc di/dt = 100a/s ?? t on forward turn-on time intrinsic turn-on time is negligible (turn-on is dominated by l s +l d ) source-drain ratings and characteristics a 8.1 35
irli520n fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics fig 1. typical output characteristics fig 3. typical transfer characteristics 0.1 1 10 100 0.1 1 10 100 i , drain-to-source current (a) d v , drain-to-source voltage (v) ds a 20s pulse w idth t = 25c j vgs top 15v 12v 10v 8.0v 6.0v 4.0v 3.0v bottom 2.5v 2.5v 0.1 1 10 100 0.1 1 10 100 i , drain-to-source current (a) d v , drain-to-source voltage (v) ds a 20s pulse w idth t = 175c vgs top 15v 12v 10v 8.0v 6.0v 4.0v 3.0v bottom 2.5v 2.5v j 0.1 1 10 100 246810 t = 25c j gs v , gate-to-source volta g e ( v ) d i , drain-to-source current (a) t = 175c j a v = 50v 20s pulse w idth ds 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 j t , junction temperature (c) r , drain-to-source o n resistance ds(on) (n orm alized) v = 10v gs a i = 10a d
irli520n fig 6. typical gate charge vs. gate-to-source voltage fig 8. maximum safe operating area fig 5. typical capacitance vs. drain-to-source voltage fig 7. typical source-drain diode forward voltage 0 200 400 600 800 1 10 100 c, capacitance (pf) ds v , drain-to-source voltage (v) a v = 0v, f = 1m hz c = c + c , c shorted c = c c = c + c gs iss gs gd ds rss gd oss ds gd c iss c oss c rss 0 3 6 9 12 15 0 5 10 15 20 25 q , total g ate charge (nc) g v , g ate-to-source voltage (v) gs v = 80v v = 50v v = 20v a for test circuit see figure 13 i = 6.0a d ds ds ds 0.1 1 10 100 0.4 0.6 0.8 1.0 1.2 1.4 t = 25c j v = 0v gs v , source-to-drain volta g e (v) i , reverse drain current (a) sd sd a t = 175c j 0.1 1 10 100 1 10 100 1000 v , drain-to-source voltage (v) ds i , drain current (a) operation in this area limited by r d ds(on) 10s 100s 1ms 10ms a t = 25c t = 175c single pulse c j
irli520n fig 10a. switching time test circuit v ds 90% 10% v gs t d(on) t r t d(off) t f fig 10b. switching time waveforms v ds pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 5.0v + - v dd fig 11. maximum effective transient thermal impedance, junction-to-case fig 9. maximum drain current vs. case temperature 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 notes: 1. duty factor d = t / t 2. peak t = p x z + t 1 2 j dm thjc c p t t dm 1 2 t , rectangular pulse duration (sec) thermal response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0.50 single pulse (thermal response) 25 50 75 100 125 150 175 0.0 2.0 4.0 6.0 8.0 10.0 t , case temperature ( c) i , drain current (a) c d
irli520n q g q gs q gd v g charge d.u.t. v ds i d i g 3ma v gs .3 m f 50k w .2 m f 12v current regulator same type as d.u.t. current sampling resistors + - 5.0 v fig 13b. gate charge test circuit fig 13a. basic gate charge waveform fig 12c. maximum avalanche energy vs. drain current fig 12b. unclamped inductive waveforms fig 12a. unclamped inductive test circuit t p v (br)dss i as 0 40 80 120 160 200 25 50 75 100 125 150 175 j e , single pulse avalanche energy (mj) as a starting t , junction temperature (c) i top 2.4a 4.2a bottom 6.0a d r g i as 0.01 w t p d.u.t l v ds + - v dd driver a 15v 10v
irli520n p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop re-applied voltage reverse recovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period + - + + + - - - fig 14. for n-channel hexfets * v gs = 5v for logic level devices peak diode recovery dv/dt test circuit ? ? ? r g v dd dv/dt controlled by r g driver same type as d.u.t. i sd controlled by duty factor "d" d.u.t. - device under test d.u.t circuit layout considerations low stray inductance ground plane low leakage inductance current transformer ? *
irli520n part number international rectifier lo go example : this is an irf1010 w ith assembly lo t c o de 9b1m assembly lo t co d e date code (yyw w ) yy = year ww = week 9246 irf1010 9b 1m a part marking information to-220 fullpak package outline to-220 fullpak outline dimensions are shown in millimeters (inches) lead assignments 1 - g a t e 2 - d r a in 3 - s o u rc e notes: 1 d im e n sio n ing & to l e r a nc in g per ansi y14.5m, 1982 2 c o n t r o ll ing d im e n s io n : in ch . d c a b minimum creepage distance betw een a-b-c-d = 4.80 (.189) 3x 2.85 (.112) 2.65 (.104) 2.80 (.110) 2.60 (.102) 4.80 (.189) 4.60 (.181) 7.10 (.280) 6.70 (.263) 3.40 (.133) 3.10 (.123) ? - a - 3.70 (.145) 3.20 (.126) 1.15 (.045) m in . 3.30 (.130) 3.10 (.122) - b - 0.90 (.035) 0.70 (.028) 3x 0.25 (.010) m a m b 2.54 (.100) 2x 3x 13.70 (.540) 13.50 (.530) 16.00 (.630) 15.80 (.622) 1 2 3 10.60 (.417) 10.40 (.409) 1.40 (.055) 1.05 (.042) 0.48 (.019) 0.44 (.017) part number international r ec tifier lo go date code (yyw w ) yy = year ww = week a ssem bly lo t co d e e401 9245 irfi840g exam ple : this is an irfi840g w ith assem bly lo t co d e e401 a world headquarters: 233 kansas st., el segundo, california 90245, tel: (310) 322 3331 european headquarters: hurst green, oxted, surrey rh8 9bb, uk tel: ++ 44 1883 732020 ir canada: 15 lincoln court, brampton, ontario l6t 3z2, tel: (905) 453 2200 ir germany: saalburgstrasse 157, 61350 bad homburg tel: ++ 49 6172 96590 ir italy: via liguria 49, 10071 borgaro, torino tel: ++ 39 11 451 0111 ir far east: 171 (k&h bldg.) 30-4 nishi-ikebukuro 3-chome, toshima-ku, tokyo japan tel: 81 33 983 0086 ir southeast asia: 315 outram road, #10-02 tan boon liat building, singapore 16907 tel: 65 221 8371 data and specifications subject to change without notice. 3/98
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